1. Field of the Invention
The present invention relates to an apparatus for detecting data included in a vertical blanking interval of a radio frequency broadcasting signal. In particular, the present invention relates to an apparatus for detecting data included in the vertical blanking interval of the radio frequency broadcasting signal, which generates a data fetch clock signal using a frequency that is twice the data transmission rate as a master clock signal, and fetches character data in accordance with the fetch clock signal.
2. Description of the Related Art
Generally, the vertical blanking interval of the radio frequency broadcasting signal means the period where no picture signal is contained. In order to efficiently use this period, research has been continually progressing in encoding a teletext signal, a caption signal, etc., in the vertical blanking interval of the broadcasting signal.
Conventionally, there have been many techniques for implementing various functions by detecting a character signal loaded in a data packet in the vertical blanking interval. Most of them fetch the data using a clock signal synchronized with a horizontal sync signal separated from a composite video signal, or using a free-running clock signal or a clock signal synchronized with a clock run-in (CRI) signal.
According to the conventional technique for synchronizing the data fetch clock signal with the horizontal sync signal, the position of the separated horizontal sync signal may vary due to the deviation of the peripheral components, and this causes the position of the data fetch clock signal synchronized with the horizontal sync signal also to vary, thereby heightening the possibility of error generation during data reception.
Meanwhile, in case of the technique using the free-running clock signal, the possibility of error generation during data reception becomes high since there is no correlation between the data and the clock signal. In case of the technique using the clock synchronized with the CRI signal contained in the sync portion of the data packet, the possibility of error generation during data reception becomes relatively low, but its circuitry becomes complicated. Also, since the frequency of the master clock signal should be much faster than the data transmission rate of the vertical blanking interval, the generation of noise which adversely affects the peripheral circuits becomes increased.
It is an object of the present invention to solve the problems involved in the related art, and to provide an apparatus for detecting data encoded in the radio frequency broadcasting signal which can reduce the possibility of error generation during data reception, simplify its circuit construction, and suppress the noise generation in the peripheral circuits by generating a data fetch clock signal using a frequency which is twice the data transmission rate as a master clock signal and by fetching character data in accordance with the fetch clock signal.
Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
In order to achieve the above and other objects, there is provided an apparatus for detecting data included in a radio frequency broadcasting signal, comprising:
a clock signal generating section for generating a predetermined fetch clock signal in response to a predetermined master clock signal and a delayed line select signal;
an enable signal generating section for receiving and delaying a line select signal, and generating the delayed line select signal in accordance with the master clock signal and a predetermined enable signal in accordance with the master clock signal and the fetch clock signal;
a data delay section for delaying serial data for a predetermined time in accordance with the master clock signal and outputting delayed serial data; and
a data conversion section for receiving the delayed serial data from the data delay section and converting the delayed serial data into parallel data in accordance with the fetch clock signal from the clock signal generating section, the enable signal from the enable signal generating section, and a reset signal.
In the present invention, a master clock which is accurately twice the data transmission rate of digital data included in the vertical blanking period, is used, and a composite sync signal is used instead of the horizontal sync signal of a phase lock loop (PLL).